| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 91 === The goal of our thesis is in consideration of the predictably severer interference to the characteristics and performances of circuits or systems even the components in VLSI chips from the RF crosstalk effects due to smaller process dimensions, quicker working frequency and lower operating voltage in future, especially in the SoC age and the Nano era.
In our thesis, consequently, we will ahead propose a completely new approach based on the concepts of unshielded twisted pair (UTP) to reduce the unwanted noise interference occurring in VLSI level and protect the whole circuit system from failure.
Our thesis is built up on the basis of UTP with the simulation under the frequency range from 1GHz to 3GHz by HFSS, and we furthermore implement our designed structures on chip through the TSMC 0.35μm logic silicide process. Eventually, for the sake of comparison with the simulation results, we adopt the on-wafer measurement by the network analyzer to eliminate the unexpected interfering factors.
In our thesis, nine different interconnection structures are presented for the purpose of contrast. Additionally, all of the interconnections are designed to be 1300μm in length to emphasize the effects of crosstalk interference. Moreover, the size of whole chip is 1750μm × 1750μm.
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