| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 91 === This thesis is proposed for designing a CMOS power amplifier with linear compensation. All designs are targeted on the standard of Bluetooth v1.0b. Three power amplifiers are conventional power amplifier, power amplifier with PMOS compensation and common-mode cancellation, and improved gm3 power amplifier. Two of these power amplifiers are designed, proposed, and measured. The improved gm3 power amplifier is in process. All are fabricated in a standard 0.25μm single-poly-five-metal CMOS process. The conventional power amplifier chip can provide 20.39dBm output power with 24% drain efficiency at 2.7GHz. The operating dc current of conventional one is 156mA from 2.5V power supply. At output power equal 20dBm, the IM3 under two-tone test is about -16.26dBc. The ACPR is about 21dB at 550kHz bandwidth. Through measured results, the performance of the proposed CMOS RF power amplifier has been verified to be well suitable for short-range communication applications and can meet Bluetooth output power level class 1(20dBm) and linearity specifications. Unfortunately, the chip with PMOS compensation and common-mode cancellation has oscillation phenomena since the design consideration non-proper. Although it still can measure out the output power and power gain, but the results are not correct enough.
From post-simulation results it can be found that these two types of power amplifier with linear compensation circuit would decrease 1~3dB output third-order intermodulation distortion at output power level equal 20dBm. When a common-mode signal exists, these two types of PA can increase 3dB IM3 values because of high CMRR value.
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