The Design and Analysis of a CMOS Low-Power 10-bit 20MS/s Pipelined Analog-to-Digital Converter
碩士 === 國立交通大學 === 電資學院學程碩士班 === 91 === In this thesis, a 10-b 20MS/s low-power CMOS pipelined analog-to-digital converter (ADC) is design and analysis. The 1.5b/stage architecture with digital error correction is used in this ADC for low-power and high-speed considerations. The prototype ADC is impl...
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| Format: | Others |
| Language: | en_US |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/20263433588930301886 |
| Summary: | 碩士 === 國立交通大學 === 電資學院學程碩士班 === 91 === In this thesis, a 10-b 20MS/s low-power CMOS pipelined analog-to-digital converter (ADC) is design and analysis. The 1.5b/stage architecture with digital error correction is used in this ADC for low-power and high-speed considerations. The prototype ADC is implemented by an input sample and hold circuit (S/H) and 9 identical unscaled pipelined stages. The power dissipation of the analog part is only 25 mW. Some circuit techniques are used to achieve low power dissipation. It includes the mismatch insensitive dynamic comparator, a capacitive reference voltage divider and a new low-power two-stage opamp.
The ADC is fabricated with TSMC 0.25um 1P5M n-well CMOS technology. The total layout area is 1974x1751 μm2. Input range of the ADC is ±1 V with 2.5 V supply voltage. Measured performance includes 0.6/-0.8LSB of DNL, 6.5/-1.5LSB of INL, 42dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 1 MHz input at 20 MS/s.
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