The Design and Analysis of a CMOS Low-Power 10-bit 20MS/s Pipelined Analog-to-Digital Converter
碩士 === 國立交通大學 === 電資學院學程碩士班 === 91 === In this thesis, a 10-b 20MS/s low-power CMOS pipelined analog-to-digital converter (ADC) is design and analysis. The 1.5b/stage architecture with digital error correction is used in this ADC for low-power and high-speed considerations. The prototype ADC is impl...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/20263433588930301886 |