Module Generator of Embedded DSP Core for Communication Applications

• Main Authors: Wei-Hao Chen, 陳威豪
• Other Authors: Shyh-Jye Jou
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/76290494907410682392

碩士 === 國立中央大學 === 電機工程研究所 === 91 === This thesis introduces the design and implementation of an embedded and parameterized digital signal processing (DSP) processor---NCU_DSP_2003. it is an enhanced version of last year version---NCU_DSP_2002. Besides providing a basic instruction set that is similar to conventional DSP processors, the enhanced capabilities include detector of the data hazard and structure hazard and do data forwarding. To enhance the operation of DSP and reduce power consumption, it provides two kinds of the nested loop instruction. These improvements make this DSP processor more efficient for computation-intensive application. The proposed parameterized DSP processor design system has some advanced features: a parameterized architecture, special functions for communication application, some low power designs and I/O for embedded consideration. We provide three kinds of Multiply-Accumulate unit for user to select according to practical applications. By using window GUI and a Verilog code generator, dedicated DSP for specified application can be generated. The chip will be implemented in a cell-based design method with a 0.25 1P5M cell library. The maximum operating frequency of a 16□16 DSP is about 170MHz.