Module Generator of Embedded DSP Core for Communication Applications
碩士 === 國立中央大學 === 電機工程研究所 === 91 === This thesis introduces the design and implementation of an embedded and parameterized digital signal processing (DSP) processor---NCU_DSP_2003. it is an enhanced version of last year version---NCU_DSP_2002. Besides providing a basic instruction set that is sim...
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ndltd-TW-091NCU054420742016-06-22T04:14:51Z http://ndltd.ncl.edu.tw/handle/76290494907410682392 Module Generator of Embedded DSP Core for Communication Applications 通訊應用之內嵌式數位訊號處理器核心產生器 Wei-Hao Chen 陳威豪 碩士 國立中央大學 電機工程研究所 91 This thesis introduces the design and implementation of an embedded and parameterized digital signal processing (DSP) processor---NCU_DSP_2003. it is an enhanced version of last year version---NCU_DSP_2002. Besides providing a basic instruction set that is similar to conventional DSP processors, the enhanced capabilities include detector of the data hazard and structure hazard and do data forwarding. To enhance the operation of DSP and reduce power consumption, it provides two kinds of the nested loop instruction. These improvements make this DSP processor more efficient for computation-intensive application. The proposed parameterized DSP processor design system has some advanced features: a parameterized architecture, special functions for communication application, some low power designs and I/O for embedded consideration. We provide three kinds of Multiply-Accumulate unit for user to select according to practical applications. By using window GUI and a Verilog code generator, dedicated DSP for specified application can be generated. The chip will be implemented in a cell-based design method with a 0.25 1P5M cell library. The maximum operating frequency of a 16□16 DSP is about 170MHz. Shyh-Jye Jou 周世傑 2003 學位論文 ; thesis 66 en_US |
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碩士 === 國立中央大學 === 電機工程研究所 === 91 ===
This thesis introduces the design and implementation of an embedded and parameterized digital signal processing (DSP) processor---NCU_DSP_2003. it is an enhanced version of last year version---NCU_DSP_2002. Besides providing a basic instruction set that is similar to conventional DSP processors, the enhanced capabilities include detector of the data hazard and structure hazard and do data forwarding. To enhance the operation of DSP and reduce power consumption, it provides two kinds of the nested loop instruction. These improvements make this DSP processor more efficient for computation-intensive application.
The proposed parameterized DSP processor design system has some advanced features: a parameterized architecture, special functions for communication application, some low power designs and I/O for embedded consideration. We provide three kinds of Multiply-Accumulate unit for user to select according to practical applications. By using window GUI and a Verilog code generator, dedicated DSP for specified application can be generated.
The chip will be implemented in a cell-based design method with a 0.25 1P5M cell library. The maximum operating frequency of a 16□16 DSP is about 170MHz.
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Shyh-Jye Jou |
author_facet |
Shyh-Jye Jou Wei-Hao Chen 陳威豪 |
author |
Wei-Hao Chen 陳威豪 |
spellingShingle |
Wei-Hao Chen 陳威豪 Module Generator of Embedded DSP Core for Communication Applications |
author_sort |
Wei-Hao Chen |
title |
Module Generator of Embedded DSP Core for Communication Applications |
title_short |
Module Generator of Embedded DSP Core for Communication Applications |
title_full |
Module Generator of Embedded DSP Core for Communication Applications |
title_fullStr |
Module Generator of Embedded DSP Core for Communication Applications |
title_full_unstemmed |
Module Generator of Embedded DSP Core for Communication Applications |
title_sort |
module generator of embedded dsp core for communication applications |
publishDate |
2003 |
url |
http://ndltd.ncl.edu.tw/handle/76290494907410682392 |
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