| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 91 ===
Recently, with the popularity of Internet and multimedia data transportation, the volume of the data transported over the Internet backbone has increased with the growth of the number of Internet users, which has stressed the need for a drastic increase in network bandwidth. Owing to the lowest loss and the highest bandwidth, optical fiber is acknowledged the most appropriate medium for wideband transmission and is a trend for Internet backbone in the future. Optical networking has become a main stream for high speed and long haul data communication. SONET OC-192 is one of the developing high speed communication systems as well as the 10Gbps Ethernet.
One of the most important factors for applying optical system to LAN is its cost. Conventionally, optical transceivers are implemented in expensive GaAs process. Nowadays, with the blooming progress in VLSI technology, several GHz front-end circuits in CMOS process have been successively demonstrated. This thesis explores circuit techniques for optical receiver front-end design in 0.18μm CMOS technology. The objective goals of this research are to realize a single chip of 1.8V 10Gbps optical receiver front-end ICs including a transimpedance amplifier and a limiting amplifier.
In the receiver front-end, the transimpedance amplifier (TIA) receives the photocurrent produced by photodiode and transforms it to voltage output. The limiting amplifier (LIA) further enlarges the tiny voltage to a fixed and sufficiently large output voltage. In order to enhance the input dynamic range, an automatic gain control circuit is included in TIA design. Under 1.8V supply voltage, the TIA provides a conversion gain of 50dBW with a —3dB bandwidth of 8GHz, and its input dynamic range is from —15dBm to 9dBm. The limiting amplifier achieves an input sensitivity of 5mv, -3dB bandwidth of 8.4GHz and conversion gain of 40dB, and the output voltage is fixed at 400mV under 1.8V voltage operation.
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