The Defect Structure of GaAs on Si Substrate Grown by Molecular Beam Epitaxy

• Main Authors: Zhao-Qing Huang, 黃兆慶
• Other Authors: Uerng-Yih Ueng
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/99775524994846282026

碩士 === 國立中山大學 === 電機工程學系研究所 === 91 === In this study, a thermodynamic model was built to apply to discuss the defect structure of GaAs epitaxial film grown on Si substrate by MBE, and it was specially focus on the GaAs/Si growth process. . It includes the initial layer, thermal treatment, epitaxial growth, n-type doping and the high temperature thermal annealing. The defect concentrations were calculated in thermal equilibrium. The result of simulation shows that defect concentration is dependent on the growth parameters such as the substrate temperature, V/III ratio and the input reactant pressure. For the GaAs/Si epitaxial process, the buffer layer was grown at low temperature with a slow growth rate but better the film. On the result of simulations, it shows that the defect concentrations decrease very slowly as the growth temperature below 450℃. So the substrate temperature selected for the initial film growth could be above 450oC. The defect structure of epitaxial layer grown pseudo-morphically at low temperature(~300℃) was beyond our calculation. The re-crystallization of epitaxial layer and the redistribution of defects were occurred during the thermal annealing process. The defect structure of GaAs epilayer were simulated as a function of arsenics pressure in the annealing process. It is expected that the Ga-rich GaAs epilayer is obtained, and the AsGa is not the dominant defect in the epilayer since AsGa is a deep energy level defect. After the buffer layer was grown, the growth temperature of GaAs epilayer could be simulated by thermodynamic analysis, and the results were obtained at 450℃~630℃. It is important to determine the growth windows of GaAs epilayer by the thermodynamic analysis, and the results of simulation were verified by several reports. The Si-doped GaAs layers are processed by thermal annealed under an arsenic overpressure. For the Si-doped level estimated to be 1018cm-3, the annealing temperature and As4 overpressure used in simulation were at 1000℃ and 10-3 ~ 10 atm, respectively. An n-type GaAs epilayer with dominant defects SiGa and SiAs were obtained under the annealing condition. For electrical characterization of GaAs epilayer, it was found that free carrier concentration, ion-scattering mobility and neutral-scattering mobility at room temperature were relate to the defect structure of GaAs epilayer, and the nature doping of GaAs epilayer grown by MBE is usually p-type. The free carrier concentration and total mobility of GaAs epilayer are about 1015cm-3 and 300 cm2/sec-V, respectively. The result of thermodynamic analysis and calculation are very close to the data reported. Typically, it is of course, as being with any theoretical analysis, often a shortage of relevant data in which to quantify the predictions. However, the calculation of thermodynamic framework and the analysis of electrical characterization could help to decrease the minimum number of experiments needed to get the most useful data.