Maximum Weight Approach for Code Synchronization in DS/SS Systems Using Adaptive Constrained Filtering Techniquewith Direct-Delay-Estimation Formula

• Main Authors: Guo-Hua Chen, 陳國華
• Other Authors: Shiunn-Jang Chern
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/49531247326154293689

碩士 === 國立中山大學 === 通訊工程研究所 === 91 === The technique of direct sequence spread spectrum (DS/SS) has been widely used in commercial mobile communication systems. The efficiency of DS/SS system is highly dependent on the accurate and fast synchronization between the incoming and locally generated PN (pseudo-noise) codes. The code synchronization is processed in two steps, acquisition (coarse alignment) and tracking (fine alignment), to bring the delay offset between the two codes. Conventionally, for code synchronization, most of techniques were proposed based on the correlation property of PN codes. Recently, the different approach, by using the adaptive LMS filtering scheme, has been proposed to reduce the hardware complexity and to improve the performance of code synchronization, especially for a long PN code. In this thesis, a new coherent adaptive code synchronization scheme is proposed, where the adaptive constrained LMS (CLMS) algorithm with the maximum tap-weight (MTW) test method is devised for code acquisition. The statistics of weight vector of the proposed CLMS scheme are derived to evaluate the performance, in terms of mean acquisition time (MAT). Analytical and simulation results verify that the proposed scheme for code acquisition outperforms the one using the conventional LMS filtering schemes, under the integer and non-integer time delay cases. Moreover, the setting of threshold value is derived for code acquisition, which is independent of the values of signal-to-noise ratio (SNR) and time delay. Next, the CLMS scheme is proposed associated with the direct delay estimation (DDE) formula for code tracking. This approach does achieve a good delay-tracking performance, which is verified via computer simulation. Simultaneously, the hardware complexity can further be reduced due to that a code-tracking loop implemented by the interpolation method is not required.