Implementation of Fading Channel Simulator
碩士 === 國立中山大學 === 通訊工程研究所 === 91 === A Rayleigh/Rician fading channel based on Jakes’ model is implemented by FPGA hardware in this thesis. Parameters, including vehicular speed, carrier frequency, quantization bits and internal clock rate, are carefully chosen according to the fading statistics. Ve...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/55955875044329422911 |
| Summary: | 碩士 === 國立中山大學 === 通訊工程研究所 === 91 === A Rayleigh/Rician fading channel based on Jakes’ model is implemented by FPGA hardware in this thesis. Parameters, including vehicular speed, carrier frequency, quantization bits and internal clock rate, are carefully chosen according to the fading statistics. Verification of this fading channel hardware is carried out on Altera FPGA board with functional and time sequential test. Finally, performance of a differential PSK modem via fading and noisy channel is simulated and emulated in both software and hardware methods.
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