Design & Implementation of a Fast Turbo Decoder

• Main Authors: Tz-Jang Wang, 王子健
• Other Authors: Tai-Lang Jong
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/26479097691144593940

碩士 === 國立清華大學 === 電機工程學系 === 91 === Turbo codes, due to its excellent capability of maintaining low bit error rate (BER) under high transmission speed and low SNR environment, are adopted in various 3GPP standards for mobile communication systems, such as CDMA 2000, WCDMA, .., etc. Recently, many research efforts have been directed toward developing efficient algorithms, architectures, and VLSI circuits for implementing the much more complicated turbo code decoder. Among many decoding algorithms, the MAP (maximum a posteriori probability) algorithm is the one with the lowest bit-error-rate and also the highest complexity. In this thesis, the focus is on the design and implementation of a high efficient MAP-based turbo decoder. All the designs have been verified using simulation as well as FPGA implementation on Altera Flex 10K100 and EP20K1000E. The main contributions of the thesis can be divided into three parts: 1. Several VLSI MAP decoder architectures with different operation control and data flow together with techniques for improving decoder circuit efficiency are proposed and analyzed. A comparison of their throughput (decoding speed) and cost (circuit area and memory usage) indicates that the proposed Two-Beta architecture has the fastest decoding speed of exceeding 4.5 Mbps and reasonable cost. 2. The relation between some parameters in the MAP algorithm, such as correcting methods of max* operation and noise variance, and BER of decoding are also analyzed with extensive simulations. Trade-offs between the circuit cost, speed, and BER can be made based on these simulation results. 3. A novel design of deinterleaver circuit is also proposed which can drastically reduce the memory usage and hence save VLSI chip area.