Parallel Architecture Design of H.264/MPEG-4 AVC Intra Coder for SDTV Applications

• Main Authors: Bing-Yu Hsieh, 謝秉諭
• Other Authors: Prof. Liang-Gee Chen
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/67235564355398011966

碩士 === 國立臺灣大學 === 電子工程學研究所 === 91 === In this thesis, we propose a parallel architecture design of H.264/MPEG-4 AVC intra coder with the capability of processing video data at SDTV (720x480x30fps) quality. It is suitable for intra coding based applications, such as DV video editing, digital still camera application, and surveillance systems. Firstly, in the system architecture design, the complexity of intra coding system is analyzed and we use a RISC model for comparison to derive the optimized parallelism for the most critical part of the system. We utilize task level interleaving scheme to accelerate the timing performance by separating the frontend encoding loop from the backend bitstream generation unit. The mode decision algorithm in H.264 reference software is modified by 4x4 DCT based transform to reduce the memory access amounts of the system. Secondly, in the hardware architecture design, we propose a reconfigurable intra predictor generator to support all 17 kinds of intra predictors in H.264/MPEG-4 AVC standard. The configuration can be reconfigured easily with simple MUX control. Decomposition technique is applied in the reconfigurable architecture to reduce the complexity of toughest plane prediction mode. Other hardware architectures, such as multi-transform engine, sequential CAVLC architecture, Q/IQ, and CGMD are also proposed to complete the intra coding system. A prototype chip is implemented by Artisan 0.25um standard CMOS cell library and fabricated by TSMC 1P5M25 technology. The chip of H.264/MPEG-4 AVC intra coder can process about 16 million pixel color images per second with about 84985 logic gate counts, die size of 3.302 x 3.312 mm2, operating frequency at 50MHz, and power consumption of 403mW under 2.5V power supply.