A GFSK Modulator by Using a Fractional-N Frequency Synthesizer

• Main Authors: Yen-Tang Chang, 張彥堂
• Other Authors: Shen-Iuan Liu
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/80797886156487215241

碩士 === 國立臺灣大學 === 電機工程學研究所 === 91 === The use of wireless products has been rapidly increasing the last few years and the new standards and technologies have been promoted and discussed over and over. Bluetooth is the one of them which was set to replace the wired equipment by the wireless communication. After the revision and the needs of the growing market, Bluetooth is believed to be one of the most important candidates for the information appliances as well as the handheld products. Although the high respect, the cost of a Bluetooth chip is still too high and this cannot meet the requirement of the worldwide market. Thus, to make the chip cost down is the most important issue for Bluetooth. The indirect modulation technique has taken place to overcome the cost problem in response to the growing demand for portable devices. This technique using a frequency synthesizer and a power-saving digital hardware without the mixer and filters required makes the cost down reality. Simulations based on this technique is created in MATLAB and verified to meet the specification of Bluetooth transmitter. There are 79 channels spreading within the ISM band defined in Bluetooth’s specification manual and it’s hard to realize for the integer-N frequency synthesizer. Thus, the fractional-N synthesizer is the effective one because the latter provides the advantages of more channels and faster settling speed under the same reference frequency. The synthesizer we take includes several building blocks: a dead-zone-minimized phase frequency detector (PFD), a charge-sharing-eliminated charge pump, a switched-capacitors voltage-controlled oscillator (VCO), and a multi-modulus divider with 64 divide numbers as well as the external loop filter. The whole chip is fabricated in 0.25µm 1P5M standard CMOS process. The chip size is 0.98 X 1.00 mm2. The other main part is the design of the digital delta-sigma modulator (DSM). FPGA is taken to verify the function of DSM for its flexibility and easy-to-synthesis. DSM which is designed as a 2nd-order MASH architecture has been proved in agreement with the simulated results of the one created in MATLAB. Finally, the integer-N, the fractional-N, and the GFSK modulation based on the compensation method are measured as well as a brief conclusion.