Digital Circuit Design of EDFT Algorithm for Power Systems

• Main Authors: Shih-Chieh Ou, 歐士傑
• Other Authors: chih-wen Liu
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/08259057367580024090

碩士 === 國立臺灣大學 === 電機工程學研究所 === 91 === This thesis focuses on the measurement unit of synchronized phasor measurement unit (PMU). PMU is used to measure the phasor and frequency parameters of voltage and current in the power systems. We design digital circuit of basic EDFT algorithm by VHDL and schematic based on FPGA instead of microprocessor in PMU. At first, we divide the mathematical formula of basic EDFT algorithm into several parts in order to set up each module, then we combine every module to complete the design of basic EDFT algorithm digital circuit by the way of bottom-up. Finally, we measure the frequency of test signal, the average error rate of our design is approximately 0.04%, and the processing time is 116.68ns.