Design and Implementation of symmetrical Half-bridge converter with Zero Voltage Switching
碩士 === 國立臺北科技大學 === 電機工程系碩士班 === 91 === This objective of this thesis is to design and implement a symmetrical half-bridge converter with zero-voltage switching. The design specifications include: 48 V for input and 3.3 V for output, and 100 W. It is well known that hard switching convert...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59760879057834465507 |
| Summary: | 碩士 === 國立臺北科技大學 === 電機工程系碩士班 === 91 === This objective of this thesis is to design and implement a symmetrical half-bridge converter with zero-voltage switching. The design specifications include: 48 V for input and 3.3 V for output, and 100 W.
It is well known that hard switching converter is with some issues, including high switching losses and significant Electro-Magnetic Interference (EMI). These issues can be coped with using soft switching technique. Moreover, the voltage un-balance issue for the input capacitors of half-bridge converter is also investigated in this thesis. A novel technique to deal with this issue is presented in the thesis.
The designed symmetrical half-bridge converter with zero-voltage switching, is implemented and the experimental results are used to verify the design. Experimental results show that the design converter achieve zero switching and balanced input voltage for input capacitors in the whole operation range.
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