High Speed Flash Analog to Digital Converter

• Main Authors: Kaih-Ping Lin, 林凱評
• Other Authors: Jung-Tang Huang
• Format: Others
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/12280330170131356783

碩士 === 國立臺北科技大學 === 機電整合研究所 === 91 === Applications of analog-to-digital converters (ADC) have become widespread as photoelectric devices, magnetic storages, and various sensors, such as light, color, temperature, and signal detectors. Furthermore, specifications of analog-to-digital converters are more stringent as a result of the growing needs for wireless network and communications, as well as photoelectric convergence and conversion knowledge. In this thesis, a flash ADC architecture is proposed to have 400 MHz samples rate with 6-bit resolution. We design the high speed architecture analog-to-digital converter by using two groups interleaved auto-zeroing technology for shortening the time period in charging to zero for each comparator. The auto-zeroing process of a comparator would keep normally its comparing operation. Also, we revise the circuit of the series resistors used for generating voltage references by adding a post amplifier to avoid effectively the distortion in voltage floating. Moreover, we instigate the democracy circuit to over on traditional bubble errors. Thus, we have not only lower the number of MOS units, but also increase the ration of bubble errors correction. We implemental the ADC in TSMC 0.25 µm 1P5M technology. The chip occupied 0.80*1.10 mm2 with both powers of 3.3V and 2.5V. Experimentally, the chip can work up to 400 MHz as the input sample of 100 MHz sin-wave and has the differential nonlinearity is DNL<0.4 LSB, the integral nonlinearity is INL<1.0 LSB ,and the efficient number of 5.03 bits in practical applications. Moreover, we use two groups interleaved auto-zeroing technology for reducing the comparators capacitor value, so we can minimize the chip size and power consumption(152mA).