| Summary: | 碩士 === 國立臺北科技大學 === 電腦通訊與控制研究所 === 91 === In the technique of JPEG2000 image compression standard, the wavelet transform (2-D DWT) plays an important role. It requires more computational power when using discrete wavelet transform. On the other hand, using the DWT implementation of VLSI can save much more computing time. As a result, the implementation of VLSI framework is very important.
In this thesis, we present an efficient architecture that performs the forward wavelet transform based on the lifting scheme. We used 5/3 filter which was established by JPEG2000.Whit three-pixels-input methodology in our architecture, it requires only one storage with the size N to compute a 2-D image of N × N, the results which are proposed in this study are less than that of JPEG2000 proposed. According to the compression results, the proposed architecture outperforms previous arts in the aspects of memory size that we can reduce 71% memory in comparison with other architectures. Besides, our design also provides embedded symmetric extension function and the latency is fixed on 5-th clock cycle. Finally, to verify the performance of our proposed architecture, we have implemented a signal chip which is constructed by the lifting scheme on 0.35μm 1P4M CMOS technology. The chip can operate the frequency up to 83 MHz and its area occupies 1.96 x 1.96 mm square.
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