Design of Wide Operating Range Delay-Locked Loop withFrequency-Selected Block
碩士 === 淡江大學 === 電機工程學系 === 91 === As the system performance and operation frequency increase rapidly, the issue of clock synchronization associates with systems becomes more important. Thus, a lot of clock synchronization, clock deskew buffer or data link technologies have been developed to handle t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/39958864060629710463 |