| Summary: | 碩士 === 淡江大學 === 電機工程學系 === 91 === In recent years, with reduction of feature size of the semiconductor process, the operating frequency of VLSI circuits has improved rapidly [1]. Specifically, the operating frequency of the high-speed systems such as wireless phones, optical fiber links, microcomputers, or the high-end system-on-a-chip (SOC), reaches GHZ range. It is required to have the high-speed clock source used in above systems. The phase-locked loop (PLL) is a mixed-signal block used in a large number of applications such as frequency synthesis, phase demodulation, clock distribution and timing recovery. It is the best circuit to generate the GHz clock for high-speed systems.With the increased operating frequency, furthermore, the testing method plays a very important role in estimating the circuit characteristics. Testing is the major obstacle to advances in mixed-signal integration. In particular, the cost for a high volume production of mixed-signal ICs is known to be essentially dominated by test development, time to test and test equipment [6]. Generally, analog circuits are tested for specifications. However, analog circuit specifications are usually very broad and verifying these specifications results in long testing time and the requirement of dedicated test equipment [6]. Specially in testing PLL circuit, there are many characteristics need to be tested, like the loop gain, frequency range, lock time, clock jitter et al. In all these characteristics, however, the clock jitter measurement and testing is the most effective method to estimate the PLL performance. This thesis is composed of two different but correlated designs. One is the phase-locked loop design. Another is the built-in jitter test technique design. In PLL circuit design, the half-digital PLL is the most popular used circuit. It has advantages of less area requirement, simpler circuit structure, et al.. However, unlike the all-digital PLL, clock jitter of the half-digital PLL circuit cannot be extracted directly by the circuit internal signal. It needs a specific jitter test circuit to measure the clock jitter of the half-digital PLL circuit. Therefore, there are two different but correlated circuits designed in this thesis.The first designed circuit is the charge pump PLL. The charge pump PLL is one of the most popular circuits. For the stability analysis, the charge pump PLL linear model is discussed with the mathematical equation. Furthermore, noise sources of the PLL circuit are also studied. It can make readers understand the circuit theory thoroughly. In this thesis, the phase-locked loop circuit is implemented with a 0.35 standard CMOS technology. And, a new phase frequency detector circuit is proposed. With the ability of lower dead zone effect, the PLL clock jitter is reduced. Furthermore, with the proposed three state PFD, the charge pump current mismatch effect also can be easily released. And, the proposed PFD circuit has a simpler structure. The PFD circuit can be operated at 1.6GHz.The second designed circuit is the built-in jitter test circuit. The basic concepts of the clock jitter measurements are discussed. The different clock jitter phenomenon is defined. Generally, the common tested clock jitter can be divided into four parts, period jitter, cycle to cycle jitter, and two different long-term jitter. Different jitter definitions play different role. For microprocessor application, period jitter might be the dominant one, which has the largest impact. Furthermore, there are four jitter test techniques introduced, one equipment based technique and three built-in test techniques. With these existed techniques, the readers would have a brief concept in clock jitter measurement techniques. Furthermore, a built-in jitter test technique is proposed. In traditional ways, the external equipment can be used to measure the analog clock signal but distort the tested clock signal seriously. In order to achieve a more convenient clock jitter measurement, a time to digital converter technique is used to output an all-digital data in the proposed method. And, the BIST concept is used to realize the proposed method. A continuous clock jitter measurement method is adopted to make a real-time measurement. With the proposed pre-delayed sample clock, no more extra delay cells are needed. The circuit area and test time can be significantly reduced. Furthermore, with an improved circuit structure, the circuit stability also can be increased and nomore external jitter-free clock is needed to sample the clock jitter.
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