An Issue Logic for Superscalar Microprocessors
碩士 === 大同大學 === 資訊工程研究所 === 91 === We tend to hardware implementation with parallelism in nowadays high performance computer. Therefore, fetch more instructions is the main bottlenecks that affect the performance. In order to enhance the performance, most part use Superscalar in nowadays...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/19973021339200645225 |
| Summary: | 碩士 === 大同大學 === 資訊工程研究所 === 91 === We tend to hardware implementation with parallelism in nowadays high performance computer. Therefore, fetch more instructions is the main bottlenecks that affect the performance. In order to enhance the performance, most part use Superscalar in nowadays microprocessor. But the Superscalar architecture is unable to enhance the performance effectively due to two reasons. One reason is complexity design will reduce the clock frequency seriously and another reason is data dependency makes the instructions parallelism unable to break through the dataflow limitation.
In our architecture, we use the wakeup and speculative wakeup logic to enhance the instructions parallelism in data dependency. In order to issue more instructions to execution every cycle, we propose the issue table to help the select logic select the suitable instructions to issue. This will improve the issue efficiency and enhance the average 22.5% performance.
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