Design of Low-Voltage CMOS Flash Analog-to-Digital Converter Based on Half-Gray Code
碩士 === 國立雲林科技大學 === 電子與資訊工程研究所碩士班 === 91 === A CMOS 8-bit, 33.3Ms/s flash ADC with 1.5V power supply is developed through the use of a low-power high-speed CMOS fully differential comparator. To achieve good signal-to-(noise and distortion) ratio in the presence of noisy digital circuitry, the...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/49028274564595354004 |
| Summary: | 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所碩士班 === 91 ===
A CMOS 8-bit, 33.3Ms/s flash ADC with 1.5V power supply is developed through the use of a low-power high-speed CMOS fully differential comparator. To achieve good signal-to-(noise and distortion) ratio in the presence of noisy digital circuitry, the architecture of the ADC is fully differential. The differential nonlinearity error in dynamical operation is less than 0.3LSB. Signal-to-noise ratio is 46.2dB at a sampling rate of 33.3MS/s and input frequency of 4MHz. The power dissipation is 106mW at 33.3MS/s with 3V power supply.
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