Low Power Non-uniform Multi-bank/channel Cache Architectures for Wire-delay Dominated Large On-Chip Caches

碩士 === 國立中正大學 === 資訊工程研究所 === 92 ===

Bibliographic Details
Main Authors:	Chih-Heng Kang, 康智恆
Other Authors:	Tien-Fu Chen
Format:	Others
Language:	en_US
Published:	2004
Online Access:	http://ndltd.ncl.edu.tw/handle/33737157880697104179

id	ndltd-TW-092CCU00392076
record_format	oai_dc
spelling	ndltd-TW-092CCU003920762016-01-04T04:08:29Z http://ndltd.ncl.edu.tw/handle/33737157880697104179 Low Power Non-uniform Multi-bank/channel Cache Architectures for Wire-delay Dominated Large On-Chip Caches 針對晶片上受金屬線延遲支配之大快取記憶體所提出之低功率非一致性多區塊/通道快取記憶體架構 Chih-Heng Kang 康智恆碩士國立中正大學資訊工程研究所 92 Tien-Fu Chen 陳添福 2004 學位論文 ; thesis 0 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 國立中正大學 === 資訊工程研究所 === 92 ===
author2	Tien-Fu Chen
author_facet	Tien-Fu Chen Chih-Heng Kang 康智恆
author	Chih-Heng Kang 康智恆
spellingShingle	Chih-Heng Kang 康智恆 Low Power Non-uniform Multi-bank/channel Cache Architectures for Wire-delay Dominated Large On-Chip Caches
author_sort	Chih-Heng Kang
title	Low Power Non-uniform Multi-bank/channel Cache Architectures for Wire-delay Dominated Large On-Chip Caches
title_short	Low Power Non-uniform Multi-bank/channel Cache Architectures for Wire-delay Dominated Large On-Chip Caches
title_full	Low Power Non-uniform Multi-bank/channel Cache Architectures for Wire-delay Dominated Large On-Chip Caches
title_fullStr	Low Power Non-uniform Multi-bank/channel Cache Architectures for Wire-delay Dominated Large On-Chip Caches
title_full_unstemmed	Low Power Non-uniform Multi-bank/channel Cache Architectures for Wire-delay Dominated Large On-Chip Caches
title_sort	low power non-uniform multi-bank/channel cache architectures for wire-delay dominated large on-chip caches
publishDate	2004
url	http://ndltd.ncl.edu.tw/handle/33737157880697104179
work_keys_str_mv	AT chihhengkang lowpowernonuniformmultibankchannelcachearchitecturesforwiredelaydominatedlargeonchipcaches AT kāngzhìhéng lowpowernonuniformmultibankchannelcachearchitecturesforwiredelaydominatedlargeonchipcaches AT chihhengkang zhēnduìjīngpiànshàngshòujīnshǔxiànyánchízhīpèizhīdàkuàiqǔjìyìtǐsuǒtíchūzhīdīgōnglǜfēiyīzhìxìngduōqūkuàitōngdàokuàiqǔjìyìtǐjiàgòu AT kāngzhìhéng zhēnduìjīngpiànshàngshòujīnshǔxiànyánchízhīpèizhīdàkuàiqǔjìyìtǐsuǒtíchūzhīdīgōnglǜfēiyīzhìxìngduōqūkuàitōngdàokuàiqǔjìyìtǐjiàgòu
_version_	1718158153720266752

Low Power Non-uniform Multi-bank/channel Cache Architectures for Wire-delay Dominated Large On-Chip Caches

Similar Items