A VLSI Implementation of High Throughput Mixed Radix FFT Processor for Low-Power/High-Speed Applications
碩士 === 國立中正大學 === 電機工程研究所 === 92 === A mixed radix shared-memory architecture that can perform FFT operation in power of 2 and reduce the clock cycle nearly by half one compared with con-ventional radix-2 FFT architecture is proposed. In addition, a simple control circuit for memory addressing gener...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/26682956384218852104 |
| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 92 === A mixed radix shared-memory architecture that can perform FFT operation in power of 2 and reduce the clock cycle nearly by half one compared with con-ventional radix-2 FFT architecture is proposed. In addition, a simple control circuit for memory addressing generation is also proposed to automatically gen-erate the butterfly sequence of mixed radix FFT processor by a counter. The main benefit of mixed radix is high throughput and then the high speed or low power consumption can be achieved. The high throughput can be utilized to achieve high speed or low power requirement. Besides, we have also proposed an IP builder for designing the FFT/IFFT based on the proposed approach. It provides a design-automation environment with parameter configurations in designing the 128~8192 points FFT/IFFT core. In order to demonstrate the proposed architec-ture, a 128 points FFT processor has been implemented in TSMC 2P4M 0.35um process and the TSMC 0.35um cell library has also been adopted. The chip size is 2583x2583mm2. The average power consumption is 77mW at 10MHz operating frequency and 3.3V supply voltage.
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