A VLSI Implementation of High Throughput Mixed Radix FFT Processor for Low-Power/High-Speed Applications
碩士 === 國立中正大學 === 電機工程研究所 === 92 === A mixed radix shared-memory architecture that can perform FFT operation in power of 2 and reduce the clock cycle nearly by half one compared with con-ventional radix-2 FFT architecture is proposed. In addition, a simple control circuit for memory addressing gener...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/26682956384218852104 |