High-Performance 1024-bits RSA Hardware Design

• Main Authors: Kai-Wen Cheng, 鄭凱文
• Other Authors: Ching-wei Yeh
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/87767704798188494972

碩士 === 國立中正大學 === 電機工程研究所 === 92 === In recent years the fast development of communication and network brings the convenience to our life. At the same time, the security of data becomes more important while transmitting. Hence, how to protect data from stealing would be a valued issue. Cryptography is the most popular method for data security. In this paper, we proposed a new algorithm of radix-4 modular multiplication known as Bit-oriented Split modular multiplication Radix-4 algorithm, or BSR4. And it is used for RSA’s modular multiplication which is the core unit of RSA cryptosystem since RSA cryptosystem is a composed of serial modular multiplications. In our work, BSR4 reduced the computing iteration from n to 1/2n (n means the length of keys) and boosted the performance to double radix-2 modular multiplication algorithm with only few more hardware cost. In the CHIP implementation, a 1024-bits RSA cryptosystem with integrated I/O was designed. We boosted the performance with the property of algorithm and optimized the large circuit. On the other hand, the design was designed with low power consideration for question of power consumption to achieving high performance and low power consumption. Design for Testability is our another emphasis, many test circuits and test methods were considered and implemented to test register and block in our RSA chip and verify our BSR4-RSA cryptosystem . With our custom standard cell library under TSMC 0.18um process, this ASIC implementation occupies an area of 2.9mm×2.9mm(IO pad included) ,takes 1008.9mW@400Mhz power consumption and achieve the high performance of 516Kbits/sec.