Temperature-Constrained Thermal-Driven Floorplan on DBL Representation

• Main Authors: Jen-jy Chen, 陳正智
• Other Authors: Jin-Tai Yan
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/59331898607652134260

碩士 === 中華大學 === 資訊工程學系碩士班 === 92 === The development of the digit circuits in recent years has already entered into the ultra large-scale integrated circuit (ULSI) and System-on-Chip (SoC) era. The design of the chip becomes more and more complicated. In order to solve increased complexity, the concept of the silicon intellectual property (SIP) modules be extensively used. Hence, the SIP modules might be designed by a lot of different companies or offered with different departments. So, the companies which develop SIP modules can make good at their development and verification of products up to the best chip operation. Good modules may form better merger chip under the state of the optimization. In addition, the circuit design becomes complicated and the function diversification of customer's demand (such as high efficiency, the low power, etc.) causes the entire IC design flow to become to need long time to finish it. Hence, an effective better floorplan approach which depends on the good data representation of floorplans, the estimation of cost function, and the sampling of process improvement becomes more and more important. In this paper, we discuss how to reduce the temperature in a floorplan. Based on the DBL representation, we propose one Temperature-Driven floorplan, named Temperature-Constrained Thermal-Driven Floorplan on DBL Representation. The DBL representation combines the advantages of representative popular representation, such as Sequence Pair, O-tree and B*-tree. The data structure of the DBL representation which accords with the demand for P-admissible characteristic, can take polynomial time to get the adjacent relations between any pair of modules, and only need to use less memory for the storage of one floorplan. Now, there is not only the discussion of the area requirement for the floorplan problem, but also the discussion of the high efficiency requirement, maximum routability requirement, hot-spot distribution…etc. Under using less area and higher density of packaging, the increasing power consumption will lead to the rising temperature. So, we can prevent from overheated temperature to cause burning or abnormal operation on one chip. By using we proposed SA-based Temperature-Constrained Thermal-Driven Floorplan on DBL Representation, the experimental results shows that our approach reduce the chip temperature and with less storage.