Hardware Implementation of Viterbi Decoder for WLAN 802.11a
碩士 === 中華大學 === 電機工程學系碩士班 === 92 === For the future, the standards of WLAN systems will be focused on the high data throughput. The IEEE 802.11a system can provide several data rates form 6 Mb/s to 54 Mb/s according to different channel quality, and thus it must attract the public notice. The aim of...
Main Author: | |
---|---|
Other Authors: | |
Format: | Others |
Language: | zh-TW |
Published: |
2004
|
Online Access: | http://ndltd.ncl.edu.tw/handle/79505787126008370885 |
Summary: | 碩士 === 中華大學 === 電機工程學系碩士班 === 92 === For the future, the standards of WLAN systems will be focused on the high data throughput. The IEEE 802.11a system can provide several data rates form 6 Mb/s to 54 Mb/s according to different channel quality, and thus it must attract the public notice. The aim of this thesis is to design a soft-decision Viterbi decoder for the IEEE 802.11a system. The decoding performances for different quantization levels of soft-decision Viterbi decoding are simulated and analyzed. Finally, the effect on the hardware complexity of decoder and the decoding performance caused by the number of quantization levels of soft-decision Viterbi decoding is analyzed and discussed.
|
---|