Micro-Power Low-Offset Integrated Circuit Design for Biomedical Signal Processing

• Main Authors: Chih-Jen Yen, 顏志仁
• Other Authors: Mely Chen Chi
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/58941630199802724982

博士 === 中原大學 === 電子工程研究所 === 92 === This study devises a hierarchical design methodology for a micro power analog processor single-chip realization and its ECG-monitoring system applications. Critical issues relating to the design of a high-performance analog processor, including offset minimization, noise performance, power consumption and process-dependent limitations, are investigated. Based on the proposed high-performance operational amplifier, all building blocks of the processor IC are constructed successfully, including an instrumentation amplifier, gain amplifier and switched-capacitor low pass filter. Design techniques are explored to enhance the circuit performance of the analog processor IC. The non-ideal offset voltage and the low-frequency noise of the instrumentation amplifier are improved using an autozero-based dynamic offset-cancellation technique involving a two-phase clocking scheme with a frequency of 20 kHz. Power dissipation is minimized using the moderate-inversion biasing operational amplifier design. The improvement of the VT reference bias circuit using the wide-swing cascode architecture provides a more accurate current for the processor IC. The analytical results demonstrate that the proposed reference generator can minimize the dependence of the operating points of operational amplifiers on process variations. Computer simulation has been undertaken using the level-49 SPICE model for every module design of the processor IC. A test chip was developed to examine the design performance using a 0.5-�慆 double-poly double-metal CMOS technology, and has a size of just 0.52 mm2. Experimental outcomes prove that the instrumentation amplifier realizes a low input offset voltage of less than 180 μV and an equivalent RMS input noise maximum of 0.67 using the autozero-based dynamic offset-cancellation technique. The analog processor IC can be operated at single supply voltage ranging between 3.3 and 5 Volts, and achieves low power consumption of 0.39 mW and 0.75 mW at supply voltages of 3.3 V and 5 V, respectively. This chip has an equivalent RMS input noise of 6.3 , a typical equivalent input offset voltage of –0.87 mV, and a bandwidth exceeding 100 Hz at a supply voltage of 5 V. A high common-mode rejection ratio and a high power-supply rejection ratio at DC are attained using the wide-swing cascode architecture. IC verification reveals that the analog processor meets the design specifications. The functions of the proposed IC have been identified using the simulated input ECG signal. Experimental results demonstrate that this processor IC is appropriate for the ECG-monitoring system applications. The advantages of low noise, low offset, low power dissipation, and minimum chip size make the analog processor IC suitable for ECG signal processing.