| Summary: | 碩士 === 朝陽科技大學 === 資訊工程系碩士班 === 92 === ABSTRACT
Phase-Locked Loop (PLL) is very popular and important in the applications of Integrated circuit field. Examples of the applications that use PLL include clock and data recovery, clock synthesis or synchronization, frequency synthesis, and PLL modulator or de-modulator applications.
The basic operating principle of PLL is to synchronize an output signal with a reference or input signal in frequency as well as phase. When the phase error between the oscillator’s output signal and the reference signal is zero, or remains constant that often called locked-stated, the condition of fast-locked is become more and more important in PLL design. In this thesis, we propose a dual-loop phase locked loop architecture which can effectively reduce the locked-time. The simulation and analysis of dual-loop phase locked loop was accomplished by using the TSMC 0.35 2P4M CMOS process. When input frequency is equal to 880 MHz in simulation, the locked time of dual-loop is 1.8 and single loop is 8.6 . Therefore, the dual-loop PLL can provide for fast locked demand.
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