Fast Multilevel Floorplanning for Large Scale Modules
碩士 === 逢甲大學 === 資訊工程所 === 92 === With the advance of deep sub-micron, current methods are not effective to obtain acceptable layout for large scale modules. Hence, it is important to provide designers of SOC with a powerful floorplanner. In traditional pproaches, it is common to simultaneously utili...
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/53485110456703914509 |
| Summary: | 碩士 === 逢甲大學 === 資訊工程所 === 92 === With the advance of deep sub-micron, current methods are not effective to obtain acceptable layout for large scale modules. Hence, it is important to provide designers of SOC with a powerful floorplanner. In traditional pproaches, it is common to simultaneously utilize clustering and declustering technologies, i.e. multiple phases to refine the solution quality. In this thesis, we propose a top-down multilevel
floorplanning algorithm to handle the floorplanning and packing for large scale modules. The algorithm is simple and only needs the clustering phase. Experimental results show significantly better running time and promising solutions in comparison with other state-of-the-art research works.
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