| Summary: | 碩士 === 輔仁大學 === 電子工程學系 === 92 === In this paper, we propose a design and implementation of a digital photo player by utilizing a high integration chip solution. To reach a higher level of performance and system flexibility, we integrate many independent components into a single chip and provide a system on chip (SOC) solution. In our design, both a JPEG Decoder and an Image Processing Unit are the kernel of the system. The JPEG decoder module includes a pipeline architecture that has the advantage of low latency and high throughput. And an Image Processing Unit is used both to zoom a decompressed picture of any resolution, based on the setting of the zoom factor, and to display the pictures on the TV. Due to the insufficient remaining bandwidth needed by SDRAM to access the pictures in the previous system, as the picture processing speed for the displaying seems slow, we propose three ways to overcome this drawback in our improved system. Overall, with the gate counts of the increased 3.3% of the previous system, our new design has an improvement of the processing speed of about 4.4 times. When measured for the ASIC prototype, our design can provide high performance and a low cost solution for potential consumer electronics.
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