Carrier recovery circuit in IEEE 802.11a WLAN

• Main Author: 陳炳志
• Other Authors: 張振豪
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/53469511796372821486

碩士 === 國立中興大學 === 電機工程學系 === 92 === Due to the growth of the electronic technology, the computer’s capability is upgraded and the transfer of information has become more and more important. The Wireless Local Area Network (WLAN) is a very popular technology for information transmission. However, the wireless network systems is transferred by the air and it would be degraded by a lot of factors including channel fading, ISI, frequency offset, phase offset, etc. To deal with these problem, it is necessary to design components such as Timing Recovery, Carrier Recovery Circuit, Equalizer, etc. In this thesis, we discuss the effects of the frequency offset and the phase offset in IEEE 802.11a baseband receiver. According to the standard specifies, its central frequency is in the 5 GHz band, and the frequency offset tolerance is +/- 20 ppm. So, the whole system has +/- 100 KHz frequency tolerance. Here, we utilize a carrier recovery circuit to remove the frequency offset between the transmitter and the receiver and to correct the phase offset of the received signal. The whole carrier recovery circuit was described in Verilog HDL code and synthesized using 0.35um 2p4m cell library. The gate counts are 43653 and the chip size is 2.6mm * 2.6mm.