VLSI Architecture Design and Implementation of Reconfigurable Computing Engine and Interconnection Network

• Main Authors: Jian-Chou Chen, 陳建洲
• Other Authors: Yeong-Kang Lai
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/49163470038722505994

碩士 === 國立中興大學 === 電機工程學系 === 92 === With the processing of the silicon technology, the main hardware cost in the chip is not occupied by the computing module but the communication between modules. The number of metal layers is increasing but the number of polycrystalline silicon layers is still one. As a result, it is important to develop an interconnection network with simple routing and low hardware cost. In this thesis, we propose an interconnection network architecture for reconfigurable computing units array. This intercon-nection network architecture supports bi-directional communication, data duplication and data reallocation, and it is scalable. The flexibility of reconfigurable computing engine is increased owing to the use of this interconnection network architecture, and thus a lot of algorithms can be mapped on the computing units easily. As the usage of the computing units increases, the performance of reconfigurable computing engine is heightened. We also propose a reconfigurable computing engine for digital signal processing. The reconfigurable computing engine is composed of eight function units, four interconnection networks, two instruction caches and two data caches. Every function units receives the instruction to perform three pipeline stages computation in order to increase the processing speed. A function unit can perform eight-bit, sixteen-bit, thirty-two-bit or sixty-four-bit operations. Taking the advantage of the communication, reallocation and duplication of the flexible interconnection networks, the reconfigurable computing engine can perform a lot of operations flexibly.