Design and Implementation of CMOS Analog Rank-Order Processing Circuits

• Main Authors: Yu-Cherng Hung, 洪玉城
• Other Authors: Bin-Da Liu
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/76127151837909556092

博士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === In this thesis, architecture designs and circuit realizations of CMOS analog signal rank-order processing are presented. Rank-order processing circuit is useful in pattern identification of artificial neural network, signals sorting, and fuzzy controller. Signal rank-order processing function includes minimum (MIN), maximum (MAX), median (MED), winner-take-all (WTA), loser-take-all (LTA), k-WTA, and arbitrary rank-order extraction. Analog output of MAX or MIN function can be obtained from the corresponding WTA or LTA digital output by using analog switches. The operation and restriction of conventional WTA/LTA architectures are initially catalogued and analyzed. With regard to speed consideration, a new CMOS self-feedback LTA circuit operated 8.3 MHz with 15-mV identifiable capability on the average is arrived by measurement. With regard to reliability consideration, a scalable high reliable WTA/LTA circuit is achieved by utilization of a single-comparator architecture. WTA or LTA function is switchable by simple logic command. The circuit is expanded to two-layer architecture to further reduce response time, and it is also shown to have a wide supply voltage range. Measured result of an experimental chip has shown that 10 mV is distinguished. Either WTA or LTA function, however, is only a single order operation. A new architecture for arbitrary rank-order extraction is designed. In CMOS sub-micro technologies, supply voltage of VLSI circuit is required to scale down in order to improve device reliability. A 1.2-V and a 1-V CMOS rank-order extractors with k-WTA capability are achieved in this thesis. Measurement results showed that the 1.2-V extractor with 40 mV resolution could operate successfully within 20 us. The 1-V extractor with 100-mV resolution is functional work within 4 us. One drawback of the extractors is that the number of the comparators required is proportional to the square of the number of inputs. The complexities of the architectures are O(N2) , where N is the number of input. In order to improve complexity, a rank-order extractor of O(N) complexity is analyzed and designed. The extractor is able to distinguish 2-uA difference among a set of input currents. Furthermore, based on bulk-driven technique, a 1-V wide-range k-WTA/k-LTA architecture is also developed, which is able to distinguish 5-mV input difference within 50 us. Using these rank-order processing circuits and a low-voltage similar measurement (SM) circuit, one application for binary pattern identification is presented. Capacitor array, switches, and exclusive NOR gates realize Hamming function. Simulation results show the circuit responds a 21-mV difference for each one-pixel difference between two binary patterns of 4 x 6 dimension. Finally, these circuits compare with other designs in open literature. These circuits allow lower supply voltage, wider input range, multiple rank-order processing capability, and higher reliability. Depending upon application requirement and system integration, these proposed circuits have much specific advantages and a larger flexibility over conventional architectures.