A Low Power Rail-to-Rail 6-bit Flash ADC Based on a Novel Complementary Average-Value approach

• Main Authors: Hui-chin Tseng, 曾慧欽
• Other Authors: Bin-Da Liu
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/98839606826471633225

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === 　　In this thesis, a 6-bit 300 MS/s flash ADC based on a novel Complementary Average-Value (CAV-Based) approach is proposed. Input signal is pre-processed and then compare with a fixed reference voltage level, which greatly simplifies the comparator design and thus saves power. In addition, rail-to-rail input range can be achieved by the technique, the offset and thus bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25-μm process parameters, the results show that INL < 0.4 LSB and DNL < 0.1LSB, and achieve 33.08 dB SNDR. The converter consumes 42 mW at 2.5 V power supply and the power efficiency of this converter is only 3.96 pJ/conv-step which compares favorably with other published results.