Reconfigurable Processor Core Design for Network-on-a-Chip

• Main Authors: Shih-Lun Chen, 陳世綸
• Other Authors: Jer-Min Jou
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/00688115726174335045

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === 　　To design a complex System-on-a-Chip (SoC) poses many challenges. The Network-on-a-Chip (NoC) provides designers a develop platform, on which they could implement various applications. After comparing and simulating several architectures of processor, the sixteen function-units processor with reconfigurable design is chosen for designing of this thesis. To combine with network interface, interconnection network, and routers, a NoC is complete. In the same way, a NoC mesh would be combined by several NoCs, network interface, interconnection network, and routers. Through hierarchical dataflow mapping, a very large special application could be mapped into a NoC mesh hierarchically. It would be more powerful, flexible, scalable, reusable and reconfigurable than traditional circuits and very high performance for special application.