| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === This thesis presents a continuous-current-mode (CCM) single-stage power factor correction (PFC) electronic ballast, which is a combination of a boost-type PFC network and a DC/AC inverter to allow CCM operation for the PFC inductor in the boost-type PFC network. Among the PFC techniques proposed in recent years, in general, the discontinuous-current-mode (DCM) single-stage PFC electronic ballasts have such drawbacks as high electromagnetic interference (EMI), high current stress, and high switching and conduction losses.
The PFC capacitor of the developed boost-type PFC network can help the PFC inductor to achieve CCM, thus shaping the input current of the proposed electronic ballast to achieve high power factor (PF).
Finally, a 36W rated power electronic ballast prototype circuit is designed and implemented. Experimental results verify the advantages of the proposed ballast; these include the following: the input current harmonics meet the IEC 61000-3-2 Class C Standard, and the ballast offers lower conducted EMI and lower current stress on switches and diodes.
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