Design and Implementation for Gb/s LVDS I/O Application

• Main Authors: shi-cun wen, 溫世存
• Other Authors: Chih-Wen Lu
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/43104917854695138443

碩士 === 國立暨南國際大學 === 電機工程學系 === 92 === In recent year, the operation speed of processor becomes faster and faster, and could deal with huger data in unit time. Therefore, it needs a giga-bit transceiver interface circuit for the transmission between peripheral equipments of computer, and application at kinds of manufactures in life, Impel I/O interface plays an important role. Low voltage differential signal (LVDS) I/O standard used for data transmission can fulfill the requirements of high speed and low power. The research of this thesis mainly utilizes low voltage differential signal technology to design 2Gb/s and low power is transmitter and receiver, A phase locked loop for testing the transceiver is also introduced. HSPICE is used to verify functions of LVDS transmitter and receiver. Then the circuits are realized by using TSMC 0.35μm 2p4m35 CMOS process provided by Chip Implementation Center. simulate result transmitter and receiver, The chip can operate functionally at 2Gb/s. Transmitter power consumption is 21mW, power consumption of the first receiver is 15mW, power consumption of the second receiver is 9mW.