Buffer Management and Switch Routing for High-Speed ATM and IP Networks

博士 === 國立交通大學 === 電信工程系 === 92 === Recent studies show that Internet traffic follows Moore's law with its volume doubled every 18 months. Via the Dense Wave-length Division Multiplexing (DWDM) transmission technology, it is now possible to carry over 300 wavelengths in a single fiber...

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Bibliographic Details
Main Authors: PO-Chou Lin, 林柏儔
Other Authors: Chung-Ju Chang
Format: Others
Language:en_US
Published: 2003
Online Access:http://ndltd.ncl.edu.tw/handle/94526706812554430698
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Summary:博士 === 國立交通大學 === 電信工程系 === 92 === Recent studies show that Internet traffic follows Moore's law with its volume doubled every 18 months. Via the Dense Wave-length Division Multiplexing (DWDM) transmission technology, it is now possible to carry over 300 wavelengths in a single fiber with per wavelength containing about 11.6 Gbps (more than 10 Gbps STM-64 line rate) payload over 7000 Km. The explosive growth of Internet traffic in the last few years has imposed tremendous stress on today's routers, particularly in the core networks. First, we discuss the VC-merging issue for Asynchronous Transfer Mode - Label Switch Routers (ATM-LSRs), which aims to solve high-speed routing through existing ATM switches. In an Multi-Protocol Label Switching (MPLS) network domain, ATM-LSRs are considered the best candidate for providing the highest forwarding capability. ATM-LSRs implement a VC-merging scheme that allows many IP routes to be mapped into the same VPI/VCI label, hence supporting scalability. We analyze the performance of an ATM-LSR with partial VC-merging capability and investigate the impact of VC-merging on the requirement of the reassembly and output buffer. The numerical computation complexity of the mathematical analysis can be reduced from O(M4) to O(M2)$, where M is the total number of ON-OFF sources. We also propose a closed-form equation, which approximates the distribution of the output buffer with satisfactory accuracy. Numerical results show that when incoming cells are severely interleaved, the VC-merging needs the reassembly buffer size to be of the same order as the output buffer size, which cannot be ignored. In the second part, we will discuss the buffer management scheme for ATM-GFR services. As discussed above, MPLS packets can be carried through ATM-LSRs by ATM variable bit rate (VBR), available bit rate (ABR), unspecified bit rate (UBR), or guarantee frame rate (GFR) virtual connections. Among all of them, GFR is the best suitable for carrying MPLS/IP packet, since it drops cells based on frame basis and can guarantee minimum cell rate (MCR). We focus on how to design a simple FIFO architecture to guarantee minimum cell rate (MCR) and share available bandwidth proportional to MCR. An efficient per-VC accounting-based scheme with steepest decent weight updating (PASD) for buffer management is presented. The PASD provides MCR guaranteed, fair share of available bandwidth to all GFR VCs, low average cell queueing delay, and efficient hardware architecture supporting up to 10 Gbps synchronous transfer mode (STM)-64 line rate. We prove that it is feasible and effective to support GFR services in ATM switches through simple FIFO queueing discipline. Finally, we discuss the IP-routing lookup scheme for Gigabit switch router (GSR) / Terabit Switch Router (TSR). A priority TCAM IP-routing lookup scheme, which combines a priority ternary content addressable memory (TCAM) technique with a compact IP-routing lookup scheme, is proposed. The priority TCAM IP-routing lookup scheme not only completes an IP-routing lookup with two memory accesses, but also achieves small lookup table size and fast table reconstruction time. The design tradeoff that an IP-routing prefix should be classified into the IP lookup memory or the priority TCAM memory is also discussed.