| Summary: | 碩士 === 國立交通大學 === 資訊工程系所 === 92 === 3D rendering applications have lots of arithmetic operations and high parallelism but execution times of each data are not the equal. General purpose computing is not fast enough for 3D rendering, Application specific computing (ASC) supports customization of applications in the form of hardware. Due to customization of hardware, this approach offers maximum performance for executing applications, but it will also cost a lot of hardware resource. In some situation with hardware constraint, it may not get high performance or even can not execute by using ASC. Reconfigurable computing can execute lots of computation with limited hardware resource and customize hardware circuit to fit the application needs for high performance.
In this thesis, I discuss how 3D rendering application can be mapped into reconfigurable system, by:
1. Analysis of rendering process: analyze operations, parallelism and computation flow
2. DFG scheduling: reuse hardware and decrease reconfigurable frequency using data parallelism to minimize total execution time
Through this, I propose a method to execute 3D rendering application on reconfigurable system.
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