An Interface Design of the ARM Bus
碩士 === 國立交通大學 === 電子工程系所 === 92 === Many applications nowadays must be combined the function of microcontroller and DSP simultaneously,so it is a very important topic to combine the two IP , DSP and microcontroller ,in SoC system to process the control and signal work simultaneously. In order to mai...
Main Authors: | , |
---|---|
Other Authors: | |
Format: | Others |
Language: | zh-TW |
Published: |
2004
|
Online Access: | http://ndltd.ncl.edu.tw/handle/t55nwy |
id |
ndltd-TW-092NCTU5427087 |
---|---|
record_format |
oai_dc |
spelling |
ndltd-TW-092NCTU54270872019-05-15T19:38:01Z http://ndltd.ncl.edu.tw/handle/t55nwy An Interface Design of the ARM Bus ARM匯流排介面之設計 Yu-Sheng Yi 易育聖 碩士 國立交通大學 電子工程系所 92 Many applications nowadays must be combined the function of microcontroller and DSP simultaneously,so it is a very important topic to combine the two IP , DSP and microcontroller ,in SoC system to process the control and signal work simultaneously. In order to maintain the high efficiency of DSP,this thesis will use higher clock cycle time of DSP than that of system to promote operating rate and achieve the goal of acceleration. In this thesis,we choose the DR8051 as our microcontroller and the ADSP2188 as our DSP. We also choose the architecture and protocol of AMBA which ARM Corporation proposed to integrate DSP and microcontroller.In order to build a basic SoC system,We not only design the microcontroller wrapper and the DSP wrapper in AMBA protocol,but also design DMA,SDRAM controller and some basic units in AMBA﹕Arbiter、Decoder and Bridge ,etc. Finally, by using microcontroller, we can control the DSP to execute a DFT program and monitor the result through the microcontroller. This architecture is accomplished by Hardware Description Language VHDL. The whole system is realized by Xilinx Corporation Virtex Ⅱ xc2v6000 FPGA. The clock cycle time of system can reach 48MHZ,The clock cycle time of DSP can reach 75MHZ. Yu-Chung Huang 黃宇中 2004 學位論文 ; thesis 77 zh-TW |
collection |
NDLTD |
language |
zh-TW |
format |
Others
|
sources |
NDLTD |
description |
碩士 === 國立交通大學 === 電子工程系所 === 92 === Many applications nowadays must be combined the function of microcontroller and DSP simultaneously,so it is a very important topic to combine the two IP , DSP and microcontroller ,in SoC system to process the control and signal work simultaneously. In order to maintain the high efficiency of DSP,this thesis will use higher clock cycle time of DSP than that of system to promote operating rate and achieve the goal of acceleration.
In this thesis,we choose the DR8051 as our microcontroller and the ADSP2188 as our DSP. We also choose the architecture and protocol of AMBA which ARM Corporation proposed to integrate DSP and microcontroller.In order to build a basic SoC system,We not only design the microcontroller wrapper and the DSP wrapper in AMBA protocol,but also design DMA,SDRAM controller and some basic units in AMBA﹕Arbiter、Decoder and Bridge ,etc. Finally, by using microcontroller, we can control the DSP to execute a DFT program and monitor the result through the microcontroller.
This architecture is accomplished by Hardware Description Language VHDL. The whole system is realized by Xilinx Corporation Virtex Ⅱ xc2v6000 FPGA. The clock cycle time of system can reach 48MHZ,The clock cycle time of DSP can reach 75MHZ.
|
author2 |
Yu-Chung Huang |
author_facet |
Yu-Chung Huang Yu-Sheng Yi 易育聖 |
author |
Yu-Sheng Yi 易育聖 |
spellingShingle |
Yu-Sheng Yi 易育聖 An Interface Design of the ARM Bus |
author_sort |
Yu-Sheng Yi |
title |
An Interface Design of the ARM Bus |
title_short |
An Interface Design of the ARM Bus |
title_full |
An Interface Design of the ARM Bus |
title_fullStr |
An Interface Design of the ARM Bus |
title_full_unstemmed |
An Interface Design of the ARM Bus |
title_sort |
interface design of the arm bus |
publishDate |
2004 |
url |
http://ndltd.ncl.edu.tw/handle/t55nwy |
work_keys_str_mv |
AT yushengyi aninterfacedesignofthearmbus AT yìyùshèng aninterfacedesignofthearmbus AT yushengyi armhuìliúpáijièmiànzhīshèjì AT yìyùshèng armhuìliúpáijièmiànzhīshèjì AT yushengyi interfacedesignofthearmbus AT yìyùshèng interfacedesignofthearmbus |
_version_ |
1719091744441630720 |