| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 92 === In this thesis, an IEEE 802.11a/g OFDM-based outer receiver design and implementation is presented. This proposed outer receiver consists of four modules. They are “Demapping”, “Deinterleaver”, “Depuncture”, and “Decoder” (Viterbi decoder), respectively. Viterbi Decoder is the main function module. According to IEEE 802.11a/g, the convolutional code 1/2 is the base coding rate. Through adopting the puncture scheme, the 802.11a/g transceiver owns several data rates. Therefore, Viterbi decoder of outer receiver needs to be modified with its structure. We also discuss the soft decision resolution and traceback-length to get the optimized solution between performance and complexity. The chip is fabricated in 0.18 um CMOS process, and the maximum throughput rate can achieve 67Mbps under clock rate 25MHz. The power consumption is below 78.83mW under 1.8V.
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