| Summary: | 博士 === 國立交通大學 === 電子工程系所 === 92 === In this dissertation, for the sake of system-on-a-chip (SOC), silicon-on-insulator (SOI) and Bipolar-CMOS-DMOS (BCD) technology have been studied because of its superior isolation characteristics and mixture of the analog functions of bipolar, digital design of CMOS and high-voltage elements of DMOS on the same chip. In order to improve breakdown voltage from less reduced-surface-field (RESURF) effect of SOI devices, the step doping profile are investigated instead of complicated linearly graded doping profile by the distinct doping region along lateral direction. In order to stride forward the future integrations on any substrates, the LTPS LDMOS using excimer laser crystallization has been demonstrated by combination of the thin film technology and power device architecture. The LTPS LDMOS at 400 C substrate heating during excimer laser annealing will be used to expect to be a future driver device in system-on-a-panel (SOP) and three-dimensional (3-D) circuit integrations. Additionally, in order to comprehend heat dissipation in 3-D integration circuits, analyses of thermal problems in 3-D circuits are necessary.
First, traditional Bipolar-CMOS-DMOS (BCD) technology, which is designed for only lateral bipolar (Bipolar, 12 V BVCEO and 25 V BVCBO), complementary metal oxide semiconductor (CMOS, 1.2 V threshold voltage) and double diffused metal oxide semiconductor (DMOS, 40 V breakdown voltage) transistors on the bulk silicon wafer, has been successfully utilized directly to fabricate silicon-on-insulator lateral-double -diffused-metal-oxide-semiconductor (SOI LDMOS) for the first time without changing any trial parameters. To simultaneously display the characteristics of high-power, high-speed and high-frequency, the results of output characteristics, switch and microwave performance must be moderate instead of individual optimum. Finally, according to the experimental results, it is proved that Bulk-BCD technology simultaneously enables high speed, high frequency and high blocking voltage applications�osuch as those in high-voltage integrated circuit switches (ns-range) and RF power amplifiers (MHz range to GHz range)�ousing a SOI wafer.
In the study of step doping profile, a partition method is proposed to analyze the high-voltage step-doping silicon on insulator lateral insulated gate bipolar transistor (Step-Doping SOI-LIGBT) structure. The on-state characteristics will be present with the similar forward voltage drop (Vce) value between the step doping and linearly graded doping devices. The breakdown voltage can be deduced by the partition mid-point method and the corresponding breakdown electric field will also be fingered out in the step drift region. Furthermore, in order to reduce the undesirable additional masks, the degraded factor (D) is developed to evaluate the minimum number of frames with the better performance. Eventually, a 660 V step analytical results will be exemplified to compare with a 606.6 V MEDICI simulation, which shows very good agreement by this proposed method.
In the study of future SOP and 3-D integrations, a new low-temperature polycrystalline silicon high-voltage LDMOS (LTPS HVLDMOS) using excimer laser crystallization has been proposed for the first time. However, in order to enhance LTPS HVLDMOS characteristics, there are two starting points: 1) integrate the thin film technology with the power device, 2) clarify the requirement of excimer laser treatment for low temperature power devices. As a result, the ON/OFF current ratio after laser treatment is improved over 106 times than that before laser treatment at Ldrift=15-�慆 and Vds=25 V. The LTPS HVLDMOS after laser treatment also demonstrates the better trade-off between the specific on resistance and breakdown voltage against the previous HVTFTs by solid phase crystallization�osuch as semi-insulating (SI), metal-field-plated (MFP), and offset-drain (OD) HVTFTs.
In order to further improve the quality of crystallized poly-Si thin films and the performance of LTPS LDMOS, low-temperature poly-Si lateral double diffused metal oxide semiconductor (LTPS LDMOS) with high voltage and very low on-resistance has been achieved using excimer laser crystallization at 400 �aC substrate heating for the first time. The ON/OFF current ratios were exhibited with 2.96 × 10^5 and 6.72 × 10^6 while operating at Vds=0.1 V and 10 V, respectively. The maximum current limit was up to 10 mA and maximum power limit could be enhanced over 1 Watt at Vds=90 V and Vgs=20 V. The Ron,sp with dimensions of W/Lch=600-um/12-um could be significantly decreased 6.67 × 102 times in the magnitude as compared with the traditional offset drain (OD) TFTs.
At last part of this thesis, the issue of heat dissipation will be discussed because many potential applications require operation at elevated temperatures. The effects of a high temperature ambient are exacerbated by power dissipation which causes additional temperature rise within the device. Power devices are often expected to run hotter than other component, but the excessive temperature rise of an inherently problem device will often lead to catastrophic failure. Failure of a single power device can shut down a computer, bring to halt a motor-driven system, or stop a vehicle dead in its tracks. This problem is anticipated to be exacerbated in 3-D circuit integration because the same power generated in a 2-D chip will now be generated in a smaller 3-D chip size resulting in a sharp increase in the power density. Therefore, accurate characterization of the thermal properties of power transistors is critical to the reliability of the systems using these devices. In order to understand this problem, the different electrical characteristics between crystalline and polycrystalline high voltage devices will be studied and the thermal stability of the LTPS LDMOS between the room temperature and 400 C irradiation will also be discussed over the ambient temperatures of 300 K�{400 K. The results of ambient temperature variation in LTPS LDMOS at 400 C irradiation are demonstrated the less sensitivity than the LTPS LDMOS before laser irradiation and at room temperature irradiation. Hence, the LTPS LDMOS at 400 C irradiation is very suitable for future system-on-a-panel (SOP) applications with higher temperature reliability.
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