Implementation of a variable length FFT processor for VDSL system

• Main Authors: Li-Yun Lin, 林麗雲
• Other Authors: Tsern-Huei Lee
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/7xjfj4

碩士 === 國立交通大學 === 電信工程系所 === 92 === Abstract In this thesis, we focus on a DMT modulation in very high-speed digital subscriber line (VDSL) communication systems. The FFT/IFFT is one of the main components in DMT systems. The IFFT can be realized by sharing hardware with the FFT hardware and so we only implement the FFT architecture. At first, we compare different FFT algorithms, and we use the radix-8 DIF FFT algorithm. The FFT lengths in VDSL are 512, 1024, 2048, 4096 and 8192 points. The radix-8 algorithm cannot deal with the 1024/2048/8192-point FFT because it only operates as an -point FFT. Therefore, we use mixed radix 8+2 and mixed radix 8+4 algorithms that can operate on 1024/2048-point data sequences using the radix-8 butterfly architecture. Before implementing the FFT hardware design, we must analyze the system requirements. There are three steps for our design flow. The first step is to determine the effective word length by using Matlab simulation. The second step is to design the architecture, which is composed of the individual components such as fft_ctrl, SRAM_model, rom_table, radix8_butterfly, address_generator, serial_parallel and fft_reorder. The third step is to verify our FFT IC design. We propose a memory-based architecture that can achieve high operating speeds and is area efficient. In addition, we design an address generation algorithm which we use in various-length FFTs. So, our proposed architecture can operate on any length FFT.