Design and Implementation of Low Jitter Logic Blocks
碩士 === 國立中央大學 === 電機工程研究所 === 92 === In the thesis, we first analyze the jitter of digital circuits. We divide the jitter source into four categories: vdd / gnd bounce jitter, substrate noise jitter, data dependent jitter, and clock jitter. For the frequently used flip-flop and MUX, we propose an ar...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/23475292915783548484 |