Design of Dynamic Frequency-Scaling Technique for Managing Power Consumption in NoC

• Main Authors: wen-tso wang, 王文佐
• Other Authors: Chun-Lung Hsu
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/44912756052065957958

碩士 === 國立東華大學 === 電機工程學系 === 92 === Power dissipation has recently emerged as one of the most critical design constraints. Especially, systems on a chip (SOCs) are rapidly evolving into large networks on a chip (NOCs), therefore unified NOC and the low power related literature research is more and more important. This paper presents a dynamically control frequency-scaling method through a power management scheme for managing the power consumption of cores in the NOC architecture. Based on the very-high-speed integrated circuit hardware description language (VHDL) and then implemented as a chip after verification with the field-programmable gate array (FPGA) implementation, the proposed power management scheme can carefully realize the frequency-scaling low-power technique. Four kind of different parts systems, respectively is FFT, uProc, MPEG2 and FIR used for demonstration, are tested and exhibit a significant reduction of the core power in a NOC when the proposed power management scheme is enabled. VHDL simulations and field-programmable gate array (FPGA) experimental results are both given to reveal that much power was saved using the proposed method.