A Study on FFT Architecture Design

• Main Authors: Chien-Ming Chen, 陳建名
• Other Authors: Chun-Chyuan Chen
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/01419264913663673533

碩士 === 國立東華大學 === 電機工程學系 === 92 === Fast Fourier transform is a key point to implement a digital signal system. Therefore, the signal processing immediately is very important.Many similarly Fourier transform algorithms are proposed after the first proposed by Cooley-Tuke in 1965. Radix-2/8 algorithm is one algorithm with low calculations of the fast Fourier transform algorithms. But the hardware implementation complexity of the Radix-2/8 algorithm increases due to the characteristics of the butterfly network. Some researches propose the shift-add for the problem of the high hardware implementation complexity caused by butterfly network. In this thesis, we propose the improved hardware implementation for the hardware complexity of the Radix-2/8 algorithm. There are two points proposed to simply hardware implement and decrease the hardware complexity. One is making use of the shift-add device to simply the hardware implement. The other is the sharing between multipliers and shift-add by changing the data sequences to decrease the numbers of the multipliers and shift-add device and reduce the hardware complexity. We implement the 32-point of Radix- 2/8 fast Fourier transform circuit on Xlinx Virtex2-x2c1000FPGA to verify the proposed. The performance of the multiplications and hardware architecture between the proposed and the convention architectures, the performance of the proposed architecture is better.