| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 92 === In this thesis, RF receiver requirements for W-CDMA user equipment are derived from the analysis of the test conditions in the recent 3GPP standard. From each test condition, we could define system-level RF characteristics such as noise figure, IIP3, phase noise, etc. On the basis of these analyses, we performed some optimization on the performance of each receiver component.
The design of an integer-N frequency synthesizer for 2-GHz W-CDMA applications is also presented in this thesis, including voltage controlled oscillator, phase frequency detector, charge pump, loop filter and divider. Realizing in a TSMC CMOS 0.18 um one-poly six-metal (1P6M) technology, the synthesizer provides a channel spacing of 5 MHz while dissipating 21.6 mW from 1.8 V power supply. The switched capacitor VCO has output frequency from 3949 MHz to 4534 MHz with phase noise -138 dBc/Hz at 8 MHz offset.
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