| Summary: | 博士 === 國立臺灣海洋大學 === 電機工程學系 === 92 === This dissertation presents the design of a CMOS RF transmitter and receiver front end. The receiver contains a low noise amplifier, a down conversion mixer, and a voltage control oscillator. While the transmitter consists of a power amplifier, an up conversion mixer, and a voltage control oscillator. All the components were designed with the TSMC CMOS high frequency models. These models were specially implemented for RF receiver and transmitter design. In receiver design, we used the inductance matching skill, band pass filter, and the DC isolation capacitance to improve the system performance. We could get less power loss along the signal path, lower overall noise, and higher gain in the low-noise amplifier circuit design. For mixer circuit design, a single square-law mixer and common source output buffer were implemented at the same time. The mixer design was focused in optimizing device size, decreasing the total circuit power consumption, and providing high linearity performance. For transmitter design, a two-stage differential power amplifier was implemented to obtain enough output power and good efficiency. A Gilbert-type mixer was used for up-conversion mixer. A local oscillator is implemented with a voltage control oscillator, and provides a quadrature output. A phase locked loop (PLL) was designed with 0.18-μm one-poly-six-metal (1P6M) TSMC CMOS process. It generated a clock signal and the operating frequency up to 5-GHz. Finally, a current control circuit was designed by varying the loads to adjust the optimum driver current. This design can help us to solve the electro-magnetic interference (EMI) problem.
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