Continuous Rate Clock and Data Recovery Circuit
碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === This thesis describes the implementation of the continuous rate clock and data recovery circuit. In order to achieve continuous rate receivable, two types of frequency tracing circuit and a wide-tuning-range VCO is developed. The CDR system incorporates the bang...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/ch9xaz |