| Summary: | 碩士 === 國立臺北科技大學 === 機電整合研究所 === 92 === With the development of RF communication technology, wireless communication devices need being much more precise and efficient in circuit design. Conventional GaAs based devices are high efficiency, low loss and low noise in high frequency and commonly applied in RF circuit. The HBT RF power amplifier could deliver power 29dBm and PAE 45%, is adequate for high power and long-distance wireless communication system. However, for low power and low move rate communication system, the CMOS technology will effectively reduce cost and exceed GaAs in integration. Fortunately, the progress of "Nano CMOS" technology enhances transistor characteristics and "RF-MEMs" technology ameliorate lumped element characteristics therefore current commercial developed power amplifiers have built in output / input matching network and include Peak-detector inside the same chip. The circuit proposed in this thesis integrating MEMs components with 2.4GHz and 5.2GHz RF CMOS power amplifier, were fabricated by standard TSMC 0.25 1P5M and UMC 0.18 1P6M CMOS process technology. The RF power amplifiers contain the power control, the peak detector and the impedance tuner to provide excursion compensation of temperature, process and load impedance. This circuit is simulated and analysed with Agilent's ADS, implemented layout with Springsoft's Laker, verified with Mentor's Calibre. This RF CMOS Power amplifier could deliver power 20dBm, PAE> 35% and power control technology could make delivered power change range from 20mW to 91mW (11dBm~19.6dBm). The impedance tuner has adjustable loading range 14<Re[ZL]<146 and -57<Im[ZL]<122. The measurement adopts on-wafer machines and FR4-PCB test boards. The whole chip area containing bond-wire pads is less than 1.1x1.1 mm2.
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